1. Field of Invention
The present invention generally relates to a method and simulator for generating phase noise, and more particularly to a method and simulator for generating phase noise in a system with a phase-locked loop when the system is simulated in time domain.
2. Description of Prior Art
Phase-locked loops (PLLs) are vital organs to many common electronic devices in a broad field of applications from wireless telecommunication to computer systems. As an example, in a modern mobile phone alone and the other applications they are prerequisite in the radio unit to transmit and receive signals. Therefore, in the digital signaling processor (DSP) computer, memory, screen and camera, the data is transmitted and processed therein and thus the phone's functionality is established.
A PLL is a regulating control system that forces the output signal of a controlled oscillator to track and be in phase with a reference input signal. A PLL is commonly used as a frequency synthesizer to generate a variable higher frequency from a lower reference frequency, where the lower reference frequency is more stable and accurate, which properties the higher frequency inherits. The controlled oscillator is the engine of the PLL. Oscillators are autonomous circuits that generate an oscillating signal.
There are many oscillator types but they all condense into one of two canonical forms, namely relaxation and harmonic oscillators. The oscillator usually consists of an amplifier in positive feedback configuration and a resonator. The amplifier provides gain to sustain oscillation by counteracting mechanical or electrical losses of the whole system. The resonator may be in form of a quarts crystal, bulk acoustic wave (BAW), micro-electro-mechanical systems (MEMS) or LC-tank circuit, which will mainly determine the operating frequency, however, likely in conjunction with other capacitors, inductors and resistors.
FIG. 1 is a block diagram of a frequency synthesizer 10. The frequency synthesizer 10 includes a PLL 11, a crystal oscillator 12, two frequency dividers 13 and 14. The crystal oscillator 12 is coupled to the frequency divider 13, the frequency divider 13 is coupled to the PLL 11, and the PLL 11 is coupled to the frequency divider 14. The PLL 11 includes a phase-frequency detection circuit 110, a charge pump circuit 111, a low pass filter 112, and a voltage-controlled oscillator 113. The phase-frequency detection circuit 110 and the charge pump circuit 111 are integrated in one block, and this block is usually called a PFD/CP block 114.
To meet the stringent requirement of many different kinds of communication systems, the frequency of a first reference signal provided by the crystal oscillator 12, is usually a very stable frequency source in its operating environment and be robust to variations in temperature, surrounding electronic components, signals and possess the quality of aging slowly. The frequency of the first reference signal often relies on its stability and quality on a quarts crystal, BAW or MEMS resonator.
The frequency divider 13 is a pre-frequency divider used to divide the frequency of the reference signal by R, so as to obtain a second reference signal. It is noted that the frequency divider 13 is not a necessary component, and can be removed in the frequency synthesizer 10. However, in order to increase the resolution of the frequency synthesizer 10, the frequency divider 13 is usually required.
The PLL 11 receives the second reference signal and the output signal of the frequency divider 14. The output signal PLL_OUT of the PLL 11 is adjusted in response to the second reference signal and a feedback signal provided by the frequency divider 14, and thus the output signal PLL_OUT of the PLL 11 inherits the phase of the second reference signal provided by the frequency divider 13. The frequency divider 14 divides the frequency of the output signal PLL OUT by N, so as to output the feedback signal.
While the frequencies, or the phases, of the feedback signal and the second reference signal are not the same, the PLL 11 adjusts the output signal PLL_OUT, and thus the frequency and phase of the feedback signal provided by frequency divider 14 are indirectly adjusted to be same as those of the second reference signal. It is noted that the dividing rates R and N may be different from each other, or equal to each other. Generally, the dividing rate N is larger than the dividing rate R, so that the frequency of the output signal PLL_OUT is higher than the frequency of the first reference signal.
The phase-frequency detector circuit 110 receives the second reference signal and the feedback signal. The phase-frequency detector circuit 110 compares both the frequencies and phases of the second reference signal and the feedback signal, and generates at least one corresponding output pulse. The charge pump circuit 111 adjusts and outputs at least one current signal in response to the output pulse output from the phase-frequency detector circuit 110. The current signal output from the charge pump circuit 111 reflects the phase and frequency deviations between the second reference signal and the feedback signal. The current signal output from the charge pump circuit 111 is then filtered by the low pass filter 112, and the low pass filter 112 outputs a filtered result having a low frequency, near DC. The voltage-controlled oscillator 113 adjusts the frequency of the output signal PLL_OUT in response to the voltage of the filtered result.
In order to simulate circuit designs on transistor level, circuit designers relies on electronic design automation (EDA) tools from, for instance, Mentor Graphics®, Cadence Design Systems Inc., or Agilent Technologies Advanced Design System (ADS). To find the phase noise, jitter or spur of a complete PLL, a transient or periodic steady state analysis must be performed, but this is time consuming and is not feasible with today's simulation tools. The main reasons are due to the complex and non-linear behavior of the entire circuit, which consists of a large number of transistors, a long transient simulation is required to capture the start-up and locking before collecting and processing data of interest, and lastly because the ratio between lowest and highest frequency, set by the integer or fractional divider ratio, imposes a numerical issue to the numerical solvers.
Mixed-signal and multi-level simulation languages alleviates the difficult nature of transient simulations of PLLs, they speed up the simulation time significantly and accurately describe the analog and digital portion of the transistor circuits represented by much simpler equivalent behavior models. One such popular behavioral language is Verilog-AMS, which is an analog and mixed signal (AMS) derivative of the Verilog hardware description language (HDL), IEEE 1364-1995 Verilog-HDL. Other simulation tools that can be used to simulate the dynamics of PLL systems and characteristics is MATLAB® and Simulink® from The MathWorks, or the PLL Noise Analyzer™ from Berkeley Design Automation Inc, to mention a few.
The PLL jitter and phase noise generation methodology has been proposed in the following references: (Ref 1) Ken Kundert, Modelling and simulation of jitter in phase-locked loops, in Analog Circuit Design: RF Analog-to-Digital Converters, Sensor and Actuator Interfaces, Low-Noise Oscillators, PLLs and Synthesizers, Kluwer Academic Publishers, November 1997; (Ref 2) A. Demir, E. Liu, A. L. Sangiovanni-Vincentelli, and I. Vassiliou, Behavioral simulation techniques for phase/delay-locked systems, in Custom Integrated Circuits Conference, 1994, Proceedings of the IEEE 1994, pages 453-456, May 1994; (Ref. 3) Ken Kundert, Modelling jitter in PLL-based frequency synthesizer, as shown in the website http://www.designer-guide.org, 2003; (Ref. 4) Predicting the phase noise and jitter of PLL-based frequency synthesizer, in Phase-Locking in High Performances, IEEE press, 2003, Behzad Razavi (editor), written in August 2002 and last updated on Aug. 30, 2006; (Ref. 5) Oskar Leuthold, System and method for simulating the noise characteristics of phase looked loops in transient analysis, U.S. Pat. No. 6,778,025.
A fast and accurate PLL jitter and phase noise methodology using Verilog for analog signals (Verilog-A) is presented in Ref. 1, which was evolved from ideas provided in Ref. 2. For each block of the PLL, transistor level simulations are performed to characterize the noise behavior. Thereafter, a single jitter value is extracted, related to white noise, and applied to each module of the entire PLL. In the Verilog-A VCO module provided in Refs. 3 and 4, each period time is extracted and saved into a file, which can be post-processed to calculate phase noise, jitter and spur corresponding to the PLL output. The principles of Refs. 1-4 involve extracting and generating the VCO phase noise data from a transient simulation and then converting the PLL blocks into behavioral-level models to simulate a PLL transient analysis, and some of these ideas later are showed up in Ref. 5.
The output from the digital VCO behavioral model provided in Ref. 5 is stored in a file and is post-processed to create noise spectrum data, as presented in Refs. 3 and 4. In Refs. 1, 3, and 4, the PLL jitter is classified as either synchronous or accumulating jitter. Synchronous jitter appears in driven circuits, like the PFD/CP block and frequency divider. It is observed as a time delay variation from an input event to an output occurrence. Accumulating jitter appears in autonomous circuits such as oscillators (including a voltage-controlled oscillator and a current-controlled oscillator), where the next output transition depends on the previous output event.
For fixed frequency oscillators the jitter can easily be modeled as a time variation of the period, and for current or voltage-controlled oscillators the jitter can be modeled as a modulated (dithered) frequency. The relation of the output and input signals of the controlled oscillator may be expressed as the following equation:
      V    out    =            sin      ⁡              (                  mnondulo          ⁡                      (                          ∫                                                                                          V                      in                                        ⁢                                          K                      VCO                                                        +                                      f                    c                                                                    1                  +                                      J                    ⁢                                                                                  ⁢                                          δ                      ⁡                                              (                                                                                                            V                              in                                                        ⁢                                                          K                              VCO                                                                                +                                                      f                            c                                                                          )                                                                                                                  )                          )              .  
The total frequency of the controlled oscillator is found by multiplying the input signal Vin by the frequency sensitivity Kvco before adding the center frequency of the oscillator fc. The frequency is then modulated by jitter, Jδ, before integrating and applying modulo to the phase argument. J represents the jitter value, and δ is a zero-mean unit-variance Gaussian random process. The modulated frequency is integrated and modulo 2π is applied to the phase argument, after which a trigonometry sinusoid function or square wave function is used to generate the output signal of the controlled oscillator.
FIG. 2 is a block diagram of a conventional apparatus 20 for simulating the system with the PLL when the phase noise is applied thereon. The conventional apparatus 20 is provided in Refs. 1, 3, and 4. The conventional apparatus 20 includes a behavior function module 201, a trigger signal generating circuit 202, a Gaussian random number generator 203, and a multiplier 204. The behavior function module 201 is coupled to the trigger signal generating circuit 202 and the multiplier 204, and the Gaussian random number generator 203 is coupled between the trigger signal generating circuit 202 and the multiplier 204.
The behavior function module 201 receives input signals and then internally generates a module signal to the trigger signal generating circuit 202. The trigger signal generating circuit 202 updates the state of the Gaussian random number generator 203 in response to the module signal. The Gaussian random number generator 203 is a zero-mean unit-variance Gaussian random number (δ) generator. The Gaussian random number δ is multiplied with the extracted jitter value J from simulations or hand-calculations, resulting in the jitter (or white noise) sequence δJ, which is injected back into the module function behavior function module 201.
FIG. 3 is a block diagram of another conventional apparatus 30 for simulating the system with the PLL when the phase noise is applied thereon. The conventional apparatus 30 includes a behavior function module 301, a trigger signal generating circuit 302, a Gaussian random number generator 303, a multiplier 304, a storage circuit 306, and a measure circuit 305. The behavior function module 301 is coupled to the trigger signal generating circuit 302, the multiplier 304, and the measure circuit 305, and the Gaussian random number generator 303 is coupled to the trigger signal generating circuit 302, the storage circuit 306, the measure circuit 305, and the multiplier 304.
The behavior function module 301, the trigger signal generating circuit 302, the Gaussian random number generator 303, and a multiplier 304 of the conventional apparatus 30 are respectively same as those of the conventional apparatus 20, and thus are not described again herein. The measure circuit 305 measures the output signal of the behavior function module 301 and the trigger signal output from the trigger signal generating circuit 302. The storage circuit 306 stores the output signal of the behavior function module 301, the trigger signal output from the trigger signal generating circuit 302, and the measure time, so as to record the noise spectrum data. Both conventional apparatuses 20 and 30 generate the phase noise and jitter for their behavior functions of their whole circuit, and this is time consuming, due to the high complexity. Therefore, it is not convenient for chip designer to obtain the performance of the circuit by the simulation with phase noise and jitter.
In Ref. 5, a method for generating a spatial noise pattern in two dimensions with a scale-invariant power spectrum with a normal error distribution is provided. Referring to FIG. 4, FIG. 4 is a flow chart of the conventional method for generating a spatial noise pattern (in time domain), which is disclosed in Ref. 5. In step S40, a set of two-dimensional frequency grids is generated, that is, a normalized frequency grid is created for each dimension. In step S41, a power spectrum is generated based on the set of the two-dimensional frequency grids. It is noted that the power spectrum in step S41 is generated for a single slope.
In step S42, a set of two-dimensional random phase shift grids is generated, and then in step S43, the set of two-dimensional random phase shift grids (complex numbers) is multiplied by the square root of the power spectrum. In step S44, an inverse fast Fourier transformation (IFFT) is performed on the multiplying result in step S43, so as to obtain a spatial noise pattern. Then in step S45, the real part of the spatial noise pattern is saved into a storage circuit. The real part of the spatial noise pattern is used to be applied on the behavior function module of the circuit, and thus the simulation with the phase noise and jitter can be carried out. However, this conventional method is used for a single slope, and in some conditions, the slope of the curve of the noise spectrum is a combination of multiple slopes.